Anaglobe -
ARM -
Helic -
Magwel -
Solido -
Sonics -
Cast -
Power Transistor Modeler (PTM)
Extract Rdson, current densities & dynamic response. PTM simulates very large power transistor arrays to extract transistor on-resistance (Rdson), identify current hot-spots and analyze electro-migration problems with 3D accuracy and unprecedented speed.

  • 3D extraction and reliability analysis of power semiconductor device
  • Extracts 3D resistance and Rdson
  • Extracts current density violations & IR drops
  • Generates distributed RC & transistor level netlists
  • Supports lateral & vertical DMOS, & IGBT devices
  • Imports layout from GDSII
  • Supports VCVS for pad stimulus
Power Transistor Modeling Family
PTM is part of a comprehensive family of tools available from Magwel for modeling all aspects of power transistor behavior and performance. Designing competitive power devices requires a thorough understanding of timing, transient and electro-thermal behavior of power transistors.
PTM-GD - Gate Delay
Switching in power transistors depends on the RC characteristics of the gate metal and poly interconnect in combination with gate oxide and junction capacitance. PTM-GD uses a highly accurate solver to extract distributed RC models for the gate interconnect and adds oxide and junction information. This information is used to predict turn-on time for power transistors that have very large gate widths.
PTM-ET - Electro-Thermal
Power transistors generate joule heating in their metal interconnect and device junctions. PTM-ET combines this with other heat sources and sinks to determine device thermal behavior. There is an interdependence between electrical behavior and thermal behavior, with each affecting the other. PTM-ET concurrently and dynamically models devices in their packaging using stimulus to provide an accurate picture during circuit operation over time.
Electro-Thermal Analysis (PTM-ET)
  • Chip/package-level 3D electro-thermal coupling and reliability analysis
  • Computes dynamic currents and Joule self-heating in metal & active area
  • Models heat flow in chip & package
  • Supports thermal planning
  • Supports non-linear temperature-dependent models
  • Self-consistent solution of electrical and thermal equations in 3D solver
  • Silicon verified accuracy
  • Imports GDSII & OpenAccess
ESD Protection Network Verification (ESDi)
  • Chip-level 3D ESD-network extraction & verification
  • Runs ESD compliance tests on all pad combinations
  • Supports multiple power / ground domains and pad groups
  • Includes layout of ESD cells in extraction
  • Reports Bus and interconnect resistances, voltage and current stress over devices and electro-migration violations
  • Fully verifies a 100 pin chip-level ESD network in under an hour
  • Supports multi-threading