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제품소개

  • EDA/IPs
  • Design Consulting

Methodics

  • AMIQ
  • AnaGlobe
  • ARM
  • PowerBaum
  • Breker
  • Cast
  • Coseda
  • Magwel
  • Onespin
  • Scientific Analog
  • TSSI

Methodics

Methodics 바로가기

Methodics

SOC Design

All IPs in a system-on-chip design-whether analog, digital, mixed-signal, software, embedded software or some combination – are fully tracked by version, hierarchy, and quality level throughout the design process, simplifting SOC assembly and providing full traceability from design ideation to final tape-out and shipment

IP Lifecycle Management

Complete IP Lifecycle Management for new, existing, and 3rd party IP enables true design reuse and traceability for any size organization and across multiple groups, sites and geographies.

Verification Traceability

Throughout the design process, verification data at each stage remains connected to the design snapshot-or releaes – that is being uesd. This assures that problems found during test can be traced back to the corresponding desgin versions and then fixes can be implemented and easily verified by version.

Functional Safety

Documented evidence of a traceable path from requirements through design to verification demonstrates that all work has been done to meet functional safety requirements such as ISO 26262 for automovie and DO-254 for aerospace.

IP Security Assurance

Every SoC is a patchwork of IPs With various origins, quality levels, and sometimes poorly understood security “attack surfaces”. Methodics solutions will help you track everything needed to assure the security of your design.

SOC Design

Platform – Providing Enterprise Traceability

Works on top of industry standard DM solutions
Enterprise wide workspace management
Release management and distribution of IP through IPLM work flow
Meta data for enterprise customization of engineering data
IP BOM Management
Integrates with other engineering systems
Analytics of entire managed environment


Seamless integration with analog design tools

Analog design is complicated enough without requiring
designer to learn new design management concepts
and methodologies.
This is why all of Methodics design management
capabilities are made available directly within existing
design environments in a natural and unobtrusive way.

Within your familiar Cadence or Synopsys environment,
designers can perform (DM) data management
operations such as check-in/check-out code,
control libraries available within a workspace,
perform releases, and with our advanced verification
capabilities even control and monitor design regressions.
The result is all the benefits of design management,
without impacting designer productivity.


Network Storage and Workspace Acceleration

Analog design is complicated enough without requiring
designer to learn new design management concepts
and methodologies.
This is why all of Methodics design management
capabilities are made available directly within existing
design environments in a natural and unobtrusive way.

Within your familiar Cadence or Synopsys environment,
designers can perform (DM) data management
operations such as check-in/check-out code,
control libraries available within a workspace,
perform releases, and with our advanced verification
capabilities even control and monitor design regressions.
The result is all the benefits of design management,
without impacting designer productivity.

대표이사 : 손민희|전화번호 : 070-4047-4060|
팩스번호 : 070-8610-7948
주소 : 서울시 서초구 청룡마을4길 11-3, 위니엠빌딩 2층|
사업자등록번호 : 215-87-33915

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