Today’s semiconductor industry faces the dynamic nature in either SOC or SIP path-finding and diversity of applications in IoT, automotive, mobile, high performance computing and even heterogeneous components integration. For example, a top-level layout assembly task normally manages hundreds of sub-blocks in either a SOC GPU chip, or an advanced-node testchip design, or a multi-chip SIP project; while each sub-block owner may have many design re-spins. High performance layout integration platform is highly desired to embrace the common challenges in chip-scale, wafer/panel-level layout integration of complicated design intents, post ECO & dummy engineering, revisions and huge data size and/or with multiple database formats.
THUNDERTM is a versatile layout integration platform to support heavy layout handling efforts from post P&R, IP merge automation & management, physical ECO verification (XOR LVL, connectivity, etc), DRC/LVS debugging interface, and even (in-line inspection) defect-to-layout mapping , failure analysis and chip-package integration (interposer vs. InFO RDL-routing, pins connectivity, etc). ThunderDB is its proprietary database, and is efficient to handle huge layout data with extreme performance of up to 600+GB GDS equivalent per minute. Users can then perform big data analysis for further processing (e.g. 3D-view, cross-section, density mapping, wafer map), machine-learning based optimization, and manipulating data from GDS, OASIS, LEF/DEF, MEBES, OpenAccess and 3rd party tools output.